SETS_FPGA.asciidoc

@@ -137,4 +137,20 @@ Depending on the settings, send by the GUI, the FPGA has to set the delay value
 
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+Table 1 shows the possible settings and its relation to the delay set by the FPGA.
+
+{empty} +
+
+
+[width="40%",frame="topbot",options="header"]
+|======================
+| *ETS FPGA-time settings*
+|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
+|5MSa/s        |Item 1
+|2        |Item 2
+|3        |Item 3
+|6        |Three items
+|======================
+.Table 1: Timing relations regarding the supported ETS sample rates
+
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