... | ... | @@ -137,4 +137,20 @@ Depending on the settings, send by the GUI, the FPGA has to set the delay value |
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Table 1 shows the possible settings and its relation to the delay set by the FPGA.
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[width="40%",frame="topbot",options="header"]
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|======================
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| *ETS FPGA-time settings*
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|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
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|5MSa/s |Item 1
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|2 |Item 2
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|3 |Item 3
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|6 |Three items
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|======================
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.Table 1: Timing relations regarding the supported ETS sample rates
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |