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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_RETS[<Random Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >
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= Sequential Equivalent Time Sampling - FPGA Implementation
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... | ... | @@ -17,4 +17,4 @@ The following sections explains how a waveform is captured and displayed using t |
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_RETS[<Random Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode>] |
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\ No newline at end of file |
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |