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removed ETS_FPGA_CONFIG.asciidoc because content is described by the GUI chapter authored by Patrick Schmitt's avatar Patrick Schmitt 
updated SETS_FPGA.asciidoc in terms of links
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SETS_FPGA.asciidoc
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_RETS[<Random Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >
= Sequential Equivalent Time Sampling - FPGA Implementation
......@@ -17,4 +17,4 @@ The following sections explains how a waveform is captured and displayed using t
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_RETS[<Random Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >