SETS_FPGA.asciidoc

@@ -144,6 +144,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 .Table 1: Timing relations regarding the supported ETS sample rates
 [frame="topbot",options="header"]
 |======================
+| 4+|*ETS FPGA-time settings*
 |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
 |5MSa/s |Item 2 |Item 3 |Item 4
 |5MSa/s |Item 2 |Item 3 |Item 4