... | ... | @@ -101,11 +101,12 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET |
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* ADC_CYCLE_START_CNT (NADC_START ) determines the amount of system clock cycles the FPGA has to wait before the ADC can be powered on.
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The FPGA will start to count the cycles after a valid trigger event was detected.
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* SIGNAL_LEARNING_CNT (NSIGNAL_LEARNING) represents the previously analysed period of the input signal. This information is represented in form of system clock cycles.
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* ADC_POWERUP_TIME (NADC_POWERUP ) is a fixed value taken from the datasheet of the ADS7885 ADC [28].
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It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
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* ADC_CYCLE_START_CNT (*NADC_START*) determines the amount of system clock cycles the FPGA has to wait before the ADC can be powered on.
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+ The FPGA will start to count the cycles after a valid trigger event was detected.
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* SIGNAL_LEARNING_CNT (*NSIGNAL_LEARNING*) represents the previously analysed period of the input signal.
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+ This information is represented in form of system clock cycles.
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* ADC_POWERUP_TIME (*NADC_POWERUP*) is a fixed value taken from the datasheet of the ADS7885 ADC [28].
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+ It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |