SETS_FPGA.asciidoc

@@ -142,7 +142,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 {empty} +
 
 .Table 1: Timing relations regarding the supported ETS sample rates
-[cols="4*", options="header"]
+[cols="4", options="header"]
 |====
 
 ^| Virtual Sample Rate