*ADC_CYCLE_START_CNT (NADC_START ) determines the amount of system clock cycles the FPGA has to wait before the ADC can be powered on.
*ADC_CYCLE_START_CNT (NADC_START ) determines the amount of system clock cycles the FPGA has to wait before the ADC can be powered on.
The FPGA will start to count the cycles after a valid trigger event was detected.
The FPGA will start to count the cycles after a valid trigger event was detected.
*SIGNAL_LEARNING_CNT (NSIGNAL_LEARNING) represents the previously analysed period of the input signal. This information is represented in form of system clock cycles.
*SIGNAL_LEARNING_CNT (NSIGNAL_LEARNING) represents the previously analysed period of the input signal. This information is represented in form of system clock cycles.
*ADC_POWERUP_TIME (NADC_POWERUP ) is a fixed value taken from the datasheet of the ADS7885 ADC [28].
*ADC_POWERUP_TIME (NADC_POWERUP ) is a fixed value taken from the datasheet of the ADS7885 ADC [28].
It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
