SETS_FPGA.asciidoc

@@ -153,7 +153,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 //|======================
 
 //Decided to insert an image of the table because asciidoc sucks
-image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=445,align="center"]
+image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=300,align="center"]
 
 {empty} +