SETS_FPGA.asciidoc

@@ -145,7 +145,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 [options="header"]
 |======================
 | 3+|*ETS FPGA-time settings*
-|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
+|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles]
 |5MSa/s |Item 2 |Item 3 |Item 4
 |5MSa/s |Item 2 |Item 3 |Item 4
 |5MSa/s |Item 2 |Item 3 |Item 4