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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_SETS[<Sequential Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
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= Random Equivalent Time Samling
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Other than the previously presented ETS method, Random Equivalent Time Sampling (RETS) continuously takes samples of the input signal. +
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The timings of the taken samples are not related to the trigger events. This leads to random taken samples of the signal in relation to the trigger events [1].
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The sampling timings of this ETS mode are derived from an internal clock. This process is illustrated in figure 1.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/ETS_RETS/ETS_RETS.JPG[caption="Figure 1: ",title="Illustration of the RETS procedure (1)",height=280,align="center"]
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The signal displayed as a dotted line in figure 1, shows the reconstructed version of the input signal. Each dot represents a captured sample.
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The signal at the bottom of figure 1 represents the pulses generated by the trigger system.
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The illustration shows that during RETS, the taken samples are not in relation to the trigger pulses.
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For reconstructing the waveform of the input signal, the time interval between capturing a sample and detecting a trigger event is important.
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The trigger event before and after capturing the sample is used to reconstruct the time dependency of the input signal.
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This will restore the temporal connection between the randomly taken samples and the time characteristics of the input signal.
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The taken samples are combined together to correctly display the captured waveform. This ETS method enables pre-trigger waveform capturing which is not possible by SETS.
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== Bibliography
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. TEKTRONIX: _XYZs of Oscilloscopes._ Primer, Tektronix, January 2016.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_SETS[<Sequential Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>] |