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updated RETS_theory.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt 
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RETS_theory.asciidoc
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_SETS[<Sequential Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | < NOT SET YET | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/GUI[Graphical User Interface>]
= Random Equivalent Time Samling
......@@ -8,7 +8,7 @@ The sampling timings of this ETS mode are derived from an internal clock. This p
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/ETS_RETS/ETS_RETS.JPG[caption="Figure 1: ",title="Illustration of the RETS procedure (1)",height=280,align="center"]
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/RETS_theory/RETS_theory.JPG[caption="Figure 1: ",title="Illustration of the RETS procedure (1)",height=280,align="center"]
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......@@ -28,4 +28,4 @@ The taken samples are combined together to correctly display the captured wavefo
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_SETS[<Sequential Equivalent Time Samling] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | < NOT SET YET | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/GUI[Graphical User Interface>]