The FPGA design of the OpenLab oscilloscope consists of several components. Those components are discussed in detail in the following sub-chapters. Furthermore, figure 1 illustrates the structure of the FPGA design and the connection of each part.
The next section will briefly describe the connections between the components of the FPGA design.
Commands and data sent by the Graphical User Interface (GUI) are received by the data communication part of the FPGA design. According to the received data, the protocol interpreter will then generate an answer. This answer will then be sent by the transmit part of the data communication entity. If the received command includes directions for other components of the FPGA, the protocol interpreter will control them accordingly.
For example, if the command "Set Channel Settings" is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO – buffer. The protocol interpreter itself then generates a reply message including the sampled data. For each oscilloscope channel there is one instance of the sampling entity, the FIFO – buffer, trigger edge detection and the ADC interface. This enables the design to simultaneously capture sample data of multiple channels. The PWM generator gets two times instantiated. The first instance handles the trigger level control. The second instance is responsible for the probe compensation.
The following weblinks will link you to the websites describing the main components of the FPGA design: