OpenLab_osci_FPGA_imp4.asciidoc

-== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
+== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[<Sampling data and triggering] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_XMC_imp[OpenLab Oscilloscope XMC Firmware>]
 
 = ADC interface
 
 This entity interfaces the serial ADC of the OpenLab FPGA based oscilloscope. The ADC interface
-is capable of controlling the ADS7885 serial ADC manufactured by Texas Instruments [28].
+is capable of controlling the ADS7885 serial ADC manufactured by Texas Instruments [1].
 This ADC does not utilize a standard interface. The chip-select input and the serial-clock of this
 component are used to control the sampling of this ADC. The ADC interface gets two times
 instantiated in order to control the ADC of channel 1 and channel 2. The entity itself consists of
@@ -11,7 +11,7 @@ three processes, each fulfilling a specific function.
 
 {empty} +
 
-Figure 45 gives an overview about the structure of the ADC-interface component.
+Figure 1 gives an overview about the structure of the ADC-interface component.
 
 {empty} +
 
@@ -22,7 +22,7 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_
 The first process, called CS_SCLK_CONTROL, controls the timing of the chip-select and the
 clock enable signal. It also sets the FIN_SPI flag in order to signalize the completion of one
 acquisition cycle. The timing of this process complies fully with the timing requirements stated
-in the datasheet of the ADS7885 serial ADC [28].
+in the datasheet of the ADS7885 serial ADC [1].
 
 {empty} +
 
@@ -41,5 +41,11 @@ accessible by the sampling-data-and-triggering entity of the FPGA design.
 
 {empty} +
 
-== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
+== Bibliography
+
+. TEXAS INSTRUMENTS: ADS7885 Data Sheet, 2008.
+
+{empty} +
+
+== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[<Sampling data and triggering] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_XMC_imp[OpenLab Oscilloscope XMC Firmware>]