This entity interfaces the serial ADC of the OpenLab FPGA based oscilloscope. The ADC interface
is capable of controlling the ADS7885 serial ADC manufactured by Texas Instruments [28].
This ADC does not utilize a standard interface. The chip-select input and the serial-clock of this
component are used to control the sampling of this ADC. The ADC interface gets two times
instantiated in order to control the ADC of channel 1 and channel 2. The entity itself consists of
three processes, each fulfilling a specific function.
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Figure 45 gives an overview about the structure of the ADC-interface component.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_ADC.PNG[caption="Figure 1: ",title="Inputs and outputs overview of the ADC-interface component",align="center"]
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The first process, called CS_SCLK_CONTROL, controls the timing of the chip-select and the
clock enable signal. It also sets the FIN_SPI flag in order to signalize the completion of one
acquisition cycle. The timing of this process complies fully with the timing requirements stated
in the datasheet of the ADS7885 serial ADC [28].
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The second process is used to split the 80MHz clock, generated by the PLL of the FPGA, to
the required 40MHz. This frequency is the operational clock rate of the ADS7885 for reaching
2.5MSPS. The process is called SCLK_CLOCK_GEN. This process is also able to completely
turn off the clock generation if ordered by the CS_SCLK_CONTROL process.
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The last process controls the transfer of each bit sent by the ADC. This process is called
READ_SAMPLE_DATA. It stores all bits in a vector signal. Due to the fact that the ADC sends
two leading zeros, the received data has to be prepared for further processing. This is done
by copying only the necessary bits of the vector to a second vector. This vector is directly
accessible by the sampling-data-and-triggering entity of the FPGA design.
