== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[<Data communication between FPGA and PC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC interface>]
= Sampling data and triggering
This entity handles the sample data acquisition of the FPGA-based oscilloscope. It also handles
the triggering and performs the advanced ETS operations. The implementation of the ETS
feature is described in chapter 7. This section will only describe the real-time sampling mode
feature is described in chapter https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation]. This section will only describe the real-time sampling mode
of this component.
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Figure 44 shows the in- and outputs of the sampling-data-and-triggering component.
Figure 1 shows the in- and outputs of the sampling-data-and-triggering component.
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@@ -41,6 +41,4 @@ entity to detect the start point of a triggered signal.
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[<Data communication between FPGA and PC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC interface>]
