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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[<Data communication between FPGA and PC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC interface>]
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= Sampling data and triggering
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This entity handles the sample data acquisition of the FPGA-based oscilloscope. It also handles
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the triggering and performs the advanced ETS operations. The implementation of the ETS
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feature is described in chapter 7. This section will only describe the real-time sampling mode
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feature is described in chapter https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation]. This section will only describe the real-time sampling mode
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of this component.
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{empty} +
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Figure 44 shows the in- and outputs of the sampling-data-and-triggering component.
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Figure 1 shows the in- and outputs of the sampling-data-and-triggering component.
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{empty} +
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... | ... | @@ -41,6 +41,4 @@ entity to detect the start point of a triggered signal. |
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[<Data communication between FPGA and PC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC interface>] |