A widely used communication type is the standard UART serial communication. The DE0 evaluation board  features a RS232 level shifter, which converts the TTL voltages from the FPGA to RS232 levels. The MAX3232 level shifter limits the maximum transfer rate to 1 MBaud which is one reason for not using this component in the OpenLab project. Students at the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage levels are not required.
For establishing a UART compatible serial communication, the FPGA design has to provide a parallel to serial data translation. In case of the OpenLab project, the SERIAL_COM_8N1 component serves as the UART interface. The component itself, as shown in figure 42, consists of two separate components which will be described in chapter 5.3.2 and 5.3.3.
This interface implementation is configured to transmit and receive data with a word size of 1 byte. The data that should be transfered to the host is given by the TX_DATA input of the SERIAL_COM_8N1 component. The transmit part then translates the information into UART compatible serial data and handles the transmission. The process of receiving data is done in a similar way. The received serial data is converted by the receive part of the SERIAL_COM_8N1 component and is provided as a 1 byte vector by RX_DATA. To start the transmission, TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer. The end of one transmission cycle is signaled by TX_FINISHED. A successfully received word is indicated by RX_FINISHED. The status of the transmit unit is shown by TX_BUSY in order to prevent data corruption.