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updated bib and fixed linking in OpenLab_osci_FPGA_imp2.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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OpenLab_osci_FPGA_imp2.asciidoc
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[<Protocol Interpreter and Reply Generator] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering>]
= Data communication between FPGA and PC = Data communication between FPGA and PC
A widely used communication type is the standard UART serial communication. A widely used communication type is the standard UART serial communication.
The DE0 evaluation board [27] features a RS232 level shifter, which converts the TTL voltages from the FPGA to RS232 levels. The DE0 evaluation board [1] features a RS232 level shifter, which converts the TTL voltages from the FPGA to RS232 levels.
The MAX3232 level shifter limits the maximum transfer rate to 1 MBaud which is one reason for not using this component in the OpenLab project. The MAX3232 level shifter limits the maximum transfer rate to 1 MBaud which is one reason for not using this component in the OpenLab project.
Students at the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage levels are not required. Students at the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage levels are not required.
...@@ -11,7 +11,7 @@ Students at the UAS Technikum Wien generally use USB to TTL serial adapter cable ...@@ -11,7 +11,7 @@ Students at the UAS Technikum Wien generally use USB to TTL serial adapter cable
For establishing a UART compatible serial communication, the FPGA design has to provide a parallel to serial data translation. For establishing a UART compatible serial communication, the FPGA design has to provide a parallel to serial data translation.
In case of the OpenLab project, the SERIAL_COM_8N1 component serves as the UART interface. In case of the OpenLab project, the SERIAL_COM_8N1 component serves as the UART interface.
The component itself, as shown in figure 42, consists of two separate components which will be described in chapter 5.3.2 and 5.3.3. The component itself, as shown in figure 1, consists of two separate components.
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...@@ -32,16 +32,16 @@ The status of the transmit unit is shown by TX_BUSY in order to prevent data cor ...@@ -32,16 +32,16 @@ The status of the transmit unit is shown by TX_BUSY in order to prevent data cor
== UART data frame == UART data frame
The UART communication transmits bytes by splitting the data into their individual bits in order to transfer them sequentially over a single transmission line. The UART communication transmits bytes by splitting the data into their individual bits in order to transfer them sequentially over a single transmission line.
Data is received by reversing the process. During idle, the transmission line is pulled high. The start of transmission is declared by sending the start bit as shown in figure 43. Data is received by reversing the process. During idle, the transmission line is pulled high. The start of transmission is declared by sending the start bit as shown in figure 2.
The receiver uses the start bit to detect the beginning of the next data package. The receiver uses the start bit to detect the beginning of the next data package.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_UART_frame.PNG[caption="Figure 1: ",title="UART data frame",height=150,align="center"] image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_UART_frame.PNG[caption="Figure 2: ",title="UART data frame",height=150,align="center"]
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The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits. The parity bit is optional and not displayed in figure 43. The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits. The parity bit is optional and not displayed in figure 2.
It can be used in order to detect corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of one transmission cycle is declared by the stop bit. It can be used in order to detect corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of one transmission cycle is declared by the stop bit.
Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate. Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate.
It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit. It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
...@@ -52,7 +52,7 @@ It declares the frequency at which one bit is transfered. Regarding the OpenLab ...@@ -52,7 +52,7 @@ It declares the frequency at which one bit is transfered. Regarding the OpenLab
The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable. The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable.
This component detects incoming data by checking continually the status of the RX line. This component detects incoming data by checking continually the status of the RX line.
If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication, which is described in section 5.3.1. If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication.
For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate. For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design
hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At
...@@ -63,7 +63,7 @@ was received, the "FINISHED" flag is set and the data is ready for further proce ...@@ -63,7 +63,7 @@ was received, the "FINISHED" flag is set and the data is ready for further proce
== Transmit Component == Transmit Component
This component is structured in a similar way as the receiving part, explained in section 5.3.2. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. This component is structured in a similar way as the receiving part. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module.
To prevent corrupted data, the transfer will only start after the "START" input signal is high. To prevent corrupted data, the transfer will only start after the "START" input signal is high.
During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid. During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
...@@ -76,8 +76,14 @@ Further tests revealed that at some host PCs during a 2 MBaud data transmission, ...@@ -76,8 +76,14 @@ Further tests revealed that at some host PCs during a 2 MBaud data transmission,
This is due to the fact that the machine was not able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten by new packets. This is due to the fact that the machine was not able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten by new packets.
In order to prevent this, the baud rate of the UART communication component can be switched between preconfigured settings. In order to prevent this, the baud rate of the UART communication component can be switched between preconfigured settings.
The baud rate can be selected between 1.2 MBaud, 1.5 MBaud and 2 MBaud. The baud rate can be selected between 1.2 MBaud, 1.5 MBaud and 2 MBaud.
As the default setting, 1.5 MBaud was chosen to be the most reliable transfer speed in relation to different kinds of PCs and operating systems. As the default setting, 1.2 MBaud was chosen to be the most reliable transfer speed in relation to different kinds of PCs and operating systems.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] == Bibliography
. TERASIC TECHNOLOGIES: DE0 User Manual, 1.6 ed., 2011.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[<Protocol Interpreter and Reply Generator] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering>]