... | @@ -46,13 +46,20 @@ It can be used in order to detect corrupted data packets, but uses bandwidth and |
... | @@ -46,13 +46,20 @@ It can be used in order to detect corrupted data packets, but uses bandwidth and |
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Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate.
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Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate.
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It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
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It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
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{empty} +
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== Receive Component
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== Receive Component
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The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable.
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The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable.
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This component detects incoming data by checking continually the status of the RX line.
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This component detects incoming data by checking continually the status of the RX line.
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If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication, which is described in section 5.3.1.
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If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication, which is described in section 5.3.1.
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For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
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For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
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For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design
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hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At
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each clock cycle one bit of the received data package is stored into a register. After the stop bit
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was received, the "FINISHED" flag is set and the data is ready for further processing.
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{empty} +
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== Transmit Component
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== Transmit Component
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... | @@ -60,6 +67,8 @@ This component is structured in a similar way as the receiving part, explained i |
... | @@ -60,6 +67,8 @@ This component is structured in a similar way as the receiving part, explained i |
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To prevent corrupted data, the transfer will only start after the "START" input signal is high.
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To prevent corrupted data, the transfer will only start after the "START" input signal is high.
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During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
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During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
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{empty} +
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== Transfer Rate and Data Integrity
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== Transfer Rate and Data Integrity
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The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2 MBaud. However, the FPGA is theoretical capable of much higher data rates.
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The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2 MBaud. However, the FPGA is theoretical capable of much higher data rates.
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... | @@ -69,4 +78,6 @@ In order to prevent this, the baud rate of the UART communication component can |
... | @@ -69,4 +78,6 @@ In order to prevent this, the baud rate of the UART communication component can |
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The baud rate can be selected between 1.2 MBaud, 1.5 MBaud and 2 MBaud.
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The baud rate can be selected between 1.2 MBaud, 1.5 MBaud and 2 MBaud.
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As the default setting, 1.5 MBaud was chosen to be the most reliable transfer speed in relation to different kinds of PCs and operating systems.
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As the default setting, 1.5 MBaud was chosen to be the most reliable transfer speed in relation to different kinds of PCs and operating systems.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] |
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] |