This interface implementation is configured to transmit and receive data with a word size of
This interface implementation is configured to transmit and receive data with a word size of 1 byte.
1 byte. The data that should be transfered to the host is given by the TX_DATA input of
The data that should be transfered to the host is given by the TX_DATA input of the SERIAL_COM_8N1 component.
the SERIAL_COM_8N1 component. The transmit part then translates the information into
The transmit part then translates the information into UART compatible serial data and handles the transmission.
UART compatible serial data and handles the transmission. The process of receiving data
The process of receiving data is done in a similar way. The received serial data is converted by the receive part of the SERIAL_COM_8N1 component and is provided as a 1 byte vector by RX_DATA.
is done in a similar way. The received serial data is converted by the receive part of the SERIAL_
To start the transmission, TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer.
COM_8N1 component and is provided as a 1 byte vector by RX_DATA. To start the transmission,
The end of one transmission cycle is signaled by TX_FINISHED. A successfully received word is indicated by RX_FINISHED.
TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer.
The status of the transmit unit is shown by TX_BUSY in order to prevent data corruption.
The end of one transmission cycle is signaled by TX_FINISHED. A successfully received
word is indicated by RX_FINISHED. The status of the transmit unit is shown by TX_BUSY in
order to prevent data corruption.
{empty} +
{empty} +
== UART data frame
== UART data frame
The UART communication transmits bytes by splitting the data into their individual bits in order
The UART communication transmits bytes by splitting the data into their individual bits in order to transfer them sequentially over a single transmission line.
to transfer them sequentially over a single transmission line. Data is received by reversing the
Data is received by reversing the process. During idle, the transmission line is pulled high. The start of transmission is declared by sending the start bit as shown in figure 43.
process. During idle, the transmission line is pulled high. The start of transmission is declared
The receiver uses the start bit to detect the beginning of the next data package.
by sending the start bit as shown in figure 43. The receiver uses the start bit to detect the
The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits.
The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits. The parity bit is optional and not displayed in figure 43.
The parity bit is optional and not displayed in figure 43. It can be used in order to detect
It can be used in order to detect corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of one transmission cycle is declared by the stop bit.
corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of
Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate.
one transmission cycle is declared by the stop bit. Depending on the configuration of the UART
It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud
rate. It declares the frequency at which one bit is transfered.
Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit
wide word, no parity bit and 1 stop bit.
== Receive Component
== Receive Component
The receiving part of the UART implementation is directly connected to the RX line of the
The receiving part of the UART implementation is directly connected to the RX line of the Transistor–Transistor Logic (TTL) serial adapter cable.
Transistor–Transistor Logic (TTL) serial adapter cable. This component detects incoming data
This component detects incoming data by checking continually the status of the RX line. If it detects an falling edge, data is being sent to the FPGA.
by checking continually the status of the RX line. If it detects an falling edge, data is being sent
This is also known as the start bit of the serial communication, which is described in section 5.3.1.
to the FPGA. This is also known as the start bit of the serial communication, which is described
For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
in section 5.3.1. For correctly interpreting the sequence of bits, the FPGA has to store the
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider.
information at the frequency of the baud rate.
At each clock cycle one bit of the received data package is stored into a register. After the stop bit was received, the "FINISHED" flag is set and the data is ready for further processing.
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design
hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At
each clock cycle one bit of the received data package is stored into a register. After the stop bit
was received, the "FINISHED" flag is set and the data is ready for further processing.
== Transmit Component
== Transmit Component
This component is structured in a similar way as the receiving part, explained in section 5.3.2.
This component is structured in a similar way as the receiving part, explained in section 5.3.2. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module.
The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. To
To prevent corrupted data, the transfer will only start after the "START" input signal is high.
prevent corrupted data, the transfer will only start after the "START" input signal is high. During
During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the
output data of the transmitter is not yet valid.
== Transfer Rate and Data Integrity
== Transfer Rate and Data Integrity
The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2
The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2 MBaud. However, the FPGA is theoretical capable of much higher data rates.
MBaud. However, the FPGA is theoretical capable of much higher data rates.
Further tests revealed that at some host PCs during a 2 MBaud data transmission, some packets sent from the FPGA were not received.
Further tests revealed that at some host PCs during a 2 MBaud data transmission, some
This is due to the fact that the machine was not able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten by new packets.
packets sent from the FPGA were not received. This is due to the fact that the machine was not
In order to prevent this, the baud rate of the UART communication component can be switched between preconfigured settings.
able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten
The baud rate can be selected between 1.2 MBaud, 1.5 MBaud and 2 MBaud.
by new packets. In order to prevent this, the baud rate of the UART communication component
As the default setting, 1.5 MBaud was chosen to be the most reliable transfer speed in relation to different kinds of PCs and operating systems.
can be switched between preconfigured settings. The baud rate can be selected between 1.2
MBaud, 1.5 MBaud and 2 MBaud. As the default setting, 1.5 MBaud was chosen to be the most
reliable transfer speed in relation to different kinds of PCs and operating systems.
