@@ -51,9 +51,7 @@ It declares the frequency at which one bit is transfered. Regarding the OpenLab
The receiving part of the UART implementation is directly connected to the RX line of the Transistor–Transistor Logic (TTL) serial adapter cable.
This component detects incoming data by checking continually the status of the RX line. If it detects an falling edge, data is being sent to the FPGA.
This is also known as the start bit of the serial communication, which is described in section 5.3.1.
For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider.
At each clock cycle one bit of the received data package is stored into a register. After the stop bit was received, the "FINISHED" flag is set and the data is ready for further processing.
