OpenLab_osci_FPGA_imp2.asciidoc

@@ -35,7 +35,7 @@ order to prevent data corruption.
 
 {empty} +
 
-== UART - data frame
+== UART data frame
 
 The UART communication transmits bytes by splitting the data into their individual bits in order
 to transfer them sequentially over a single transmission line. Data is received by reversing the
@@ -58,7 +58,7 @@ rate. It declares the frequency at which one bit is transfered.
 Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit
 wide word, no parity bit and 1 stop bit.
 
-== Receive - Component
+== Receive Component
 
 The receiving part of the UART implementation is directly connected to the RX line of the
 Transistor–Transistor Logic (TTL) serial adapter cable. This component detects incoming data
@@ -71,7 +71,7 @@ hast to be clocked down to 1 MHz. This is done by implementing a simple clock di
 each clock cycle one bit of the received data package is stored into a register. After the stop bit
 was received, the "FINISHED" flag is set and the data is ready for further processing.
 
-== Transmit - Component
+== Transmit Component
 
 This component is structured in a similar way as the receiving part, explained in section 5.3.2.
 The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. To