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try to fix OpenLab_osci_FPGA_imp2.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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OpenLab_osci_FPGA_imp2.asciidoc
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......@@ -48,9 +48,8 @@ It declares the frequency at which one bit is transfered. Regarding the OpenLab
== Receive Component
The receiving part of the UART implementation is directly connected to the RX line of the Transistor–Transistor Logic (TTL) serial adapter cable.
This component detects incoming data by checking continually the status of the RX line. If it detects an falling edge, data is being sent to the FPGA.
This is also known as the start bit of the serial communication, which is described in section 5.3.1.
The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable.
== Transmit Component
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