... | ... | @@ -125,4 +125,19 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_ |
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{empty} +
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As shown in figure 41, the state machine itself can reach the following states:
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{empty} +
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* START
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By powering up the FPGA design the state machine will start execution at this state.
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This state is used to generate a dummy message. The dummy message is two bytes in
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size and does not comply to any valid command or reply. It initializes the data path of
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generating reply messages and prevents corrupted data during the power up phase. The
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values of the two dummy bytes are considered as dont care. This state is only reached
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once during power up and cannot be reached during normal operation.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] |