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  • OpenLab_osci_FPGA_imp1

OpenLab_osci_FPGA_imp1 · Changes

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fixed linking in OpenLab_osci_FPGA_imp1.asciidoc authored Mar 13, 2017 by Patrick Schmitt's avatar Patrick Schmitt
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OpenLab_osci_FPGA_imp1.asciidoc
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp[<OpenLab Oscilloscope FPGA IP-Core] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA and PC>]
= Protocol Interpreter and Reply Generator
......@@ -344,4 +344,4 @@ flag is set by the Command Execution State Machine.
{empty} +
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp[<OpenLab Oscilloscope FPGA IP-Core] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA and PC>]
Clone repository
  • ETS_theory
  • OpenLab_RCL_uC_imp
  • OpenLab_SignalToolkit
  • OpenLab_UI_source_uC_imp
  • OpenLab_firm_ip_intro
  • OpenLab_logic_uC_imp
  • OpenLab_osci_FPGA_imp
  • OpenLab_osci_FPGA_imp1
  • OpenLab_osci_FPGA_imp2
  • OpenLab_osci_FPGA_imp3
  • OpenLab_osci_FPGA_imp4
  • OpenLab_osci_LPC_imp
  • OpenLab_osci_TIVAC_imp
  • OpenLab_osci_XMC_imp
  • OpenLab_siggen_ATMEL_imp
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