OpenLab_osci_FPGA_imp.asciidoc

+== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
+
+= OpenLab Oscilloscope FPGA IP-Core
+
+The FPGA design of the OpenLab oscilloscope consists of several components. Those components are discussed in detail in the following sub-chapters.
+Furthermore, figure 1 illustrates the structure of the FPGA design and the connection of each part.
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+image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_overview.PNG[caption="Figure 1: ",title="FPGA design overview of the OpenLab oscilloscope",height=280,align="center"]
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+The next section will briefly describe the connections between the components of the FPGA design.
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+
+== FPGA Design Overview
+
+Commands and data sent by the Graphical User Interface (GUI) are received by the data communication part of the FPGA design.
+According to the received data, the protocol interpreter will then generate an answer. This answer will then be sent by the transmit part of the data communication entity.
+If the received command includes directions for other components of the FPGA, the protocol interpreter will control them accordingly.
+
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+For example, if the command “Set Channel Settings” is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO – buffer.
+The protocol interpreter itself then generates a reply message including the sampled data.
+For each oscilloscope channel there is one instance of the sampling entity, the FIFO – buffer, trigger edge detection and the ADC interface.
+This enables the design to simultaneously capture sample data of multiple channels. The PWM generator gets two times instantiated.
+The first instance handles the trigger level control. The second instance is responsible for the probe compensation.
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+The following weblinks will link you to the websites describing the main components of the FPGA design:
+
+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[Protocol Interpreter and Reply Generator]
+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA & PC]
+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering]
+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC - interface]
+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp5[Trigger edge detect]
+
+{empty} +
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+== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]