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  • OpenLab_osci_FPGA_imp

OpenLab_osci_FPGA_imp · Changes

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fixed bad symbol in OpenLab_osci_FPGA_imp.asciidoc authored Mar 09, 2017 by Patrick Schmitt's avatar Patrick Schmitt
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OpenLab_osci_FPGA_imp.asciidoc
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......@@ -34,7 +34,7 @@ The first instance handles the trigger level control. The second instance is res
The following weblinks will link you to the websites describing the main components of the FPGA design:
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[Protocol Interpreter and Reply Generator]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA & PC]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA and PC]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC - interface]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp5[Trigger edge detect]
......
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  • ETS_theory
  • OpenLab_RCL_uC_imp
  • OpenLab_SignalToolkit
  • OpenLab_UI_source_uC_imp
  • OpenLab_firm_ip_intro
  • OpenLab_logic_uC_imp
  • OpenLab_osci_FPGA_imp
  • OpenLab_osci_FPGA_imp1
  • OpenLab_osci_FPGA_imp2
  • OpenLab_osci_FPGA_imp3
  • OpenLab_osci_FPGA_imp4
  • OpenLab_osci_LPC_imp
  • OpenLab_osci_TIVAC_imp
  • OpenLab_osci_XMC_imp
  • OpenLab_siggen_ATMEL_imp
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