getting-started-zybo.md

@@ -5,13 +5,13 @@
 
 ***
 
-# 5. Getting Started - Zybo
+# 5.2 Getting Started - Zybo
 
-## 5.1 Introduction
+## 5.2.1 Introduction
 
 The following section presents a tutorial for the Zybo Development Board. 
 
-### 5.1.1  Pre-requisites
+### 5.2.1.1  Pre-requisites
 
 Following pre-requisites are necessary in order to work through this tutorial:
 
@@ -21,17 +21,17 @@ Following pre-requisites are necessary in order to work through this tutorial:
 
 **Note:** Vivado 2016.1 was successfully tested with this tutorial.
 
-### 5.1.2 Download the Design files
+### 5.2.1.2 Download the Design files
 
 An archive with the design files can be downloaded [here](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/designfiles/GettingStartedZybo.zip). Furthermore, download the [board definition files](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/designfiles/BoardFilesZybo.zip) for the Zybo development Board. Extract the archive and copy the folder **zybo** to following directory:
 
 **$VIVADO_ROOT_DIR$/Vivado/2015.4/data/boards/board_files**
 
-## 5.2 Tutorial
+## 5.2.2 Tutorial
 
-This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Then the project will be exported to Xinlinx SDK, where a simple blink led application will be created. Furthermore, the board setup will be explained. Finally, the Bitstream will be flashed onto the FPGA and the application will be tested.
+This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Then the project will be exported to Xinlinx SDK, where a simple blink led application will be created. Furthermore, the board setup will be explained. Finally, the Bitstream will be downloaded to the FPGA and the application will be tested.
 
-### 5.2.1  Building the Bitstream
+### 5.2.2.1  Building the Bitstream
 
 _1. Launch Vivado:_
 
@@ -128,7 +128,7 @@ Finally, click on **File -> Launch SDK**. Leave both options at **<Local to proj
 
 This concludes the Hardware generation process. 
 
-### 5.2.2 Xilinx SDK
+### 5.2.2.2 Xilinx SDK
 
 Click on **File -> New -> Application Project** to create a new project. As project name enter **blink_led**. Leave all other options at their default values. Click **Next**. 
 
@@ -151,7 +151,7 @@ Browse to the location of the downloadand and extracted GettingStartedZybo.zip f
 ![](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/img/tutorial_zybo22.png)
 
 
-### 5.2.3 Board Setup
+### 5.2.2.3 Board Setup
 
 Make sure that **JP14** is configured to use **USB** as power source. Furthermore, make sure **JP5** is configured to the **JTAG** mode. Insert a micro USB cable to **J11** and connect it to your PC. Make sure that the switches **SW0 - SW15** are in the off position.
 
@@ -160,7 +160,7 @@ Make sure that **JP14** is configured to use **USB** as power source. Furthermor
 ![](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/img/GettingStartedZyboHW.png)
 
 
-### 5.2.4 Test the Application
+### 5.2.2.4 Test the Application
 
 Right click on the **blink_led** project and click on **Run as -> Run Configurations**. Double click on **Xilinx C/C++ application (GDB)**.
 
@@ -174,7 +174,7 @@ Click **Apply**, then click **Close**. Now Click on **Xilinx Tools -> Program FP
 
 ![](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/img/tutorial_zybo25.png)
 
-After the bitstream is sucessfully flashed onto the FPGA the **DONE LED** (**LD10**) lights up.  Now click on the **run** Button the start the application. 
+After the bitstream is sucessfully donwoloaded to the FPGA the **DONE LED** (**LD10**) lights up.  Now click on the **run** Button the start the application. 
 
 ![](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-zybo/img/tutorial_zybo26.png)