This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Then the project will be exported to Xinlinx SDK, where a simple blink led application will be created. Furthermore, the board setup will be explained. Finally, the Bitstream will be downloaded to the FPGA and the application will be tested.
Click on the Create New Project button in the quick start menu. Click Next. Enter blink_led_zybo as the Project name. Make sure that Create project subdirectory is checked. Click Next.
Note: Do not use spaces or special characters in the project path.
Select RTL Project. Make sure that the Do not specify sources at this time checkbox is selected. Click Next.
In the select box click on Boards. Select Zybo and click Next.
Click Finish to finish the project creation process.
In the Flow Navigator toolbar click the Create Block Design button which can be found in the IP Integrator subsection.
Set name to blink_led_zybo_bd and click OK.
In the Diagram of the newly created block design right click anywhere. Click Add IP and type in Zynq. Double click on ZYNQ7 Processing System.
Click on Run Block Automation on the topside of the diagram pane.
A window pops up. Leave the default options and click OK.
Click on the IP Settings button on the leftside.
Click on the Repository Manager tab, then click on the plus button to add the blink led IP Core.
Browse to the extracted GettingStartedZybo.zip folder and click OK. A window pops up, click OK. Click OK to leave the Project Settings.
Right click on empty space in the diagram pane. Click Add IP and type in blink_led. Double click on blink_led_v1.0.
Click on Run ConnectionAutomation on the topside of the diagram pane. A window pops up. Leave the default options and click OK.
Double Click on processing_system7_0 block. Click on MIO Configurations. Click on the button shown below to expand all peripherals. Deselect all peripherals except UART1. Click OK.
Right click on empty space in the diagram pane. Click Create Port. For Port name type leds_out. Set the Direction to Output. Leave the Type as Other. Check the Create vector checkbox. Type from 3 to 0.
Hold the mouse over the newly created leds_out[3:0] port until the cursor changes to apencil. Hold the left mouse down and move the cursor to the
leds_out[3:0] port of the blink_led_0 block until the connection is established, then let go of the left mouse.
In the design tab click on Sources. Right click on Constraints and click on Add Sources. Make sure that Add or create constraints is checked. Click Next.
Click on Add Files. Browse to the location of the downloadand extracted GettingStartedZybo.zip file. Select blink_led.xdc and click OK. Click Finish.
In the Sources tab right click on blink_led_zybo_bd and click on Generate Output Products. A window pops up, click on Generate. After completion click on OK.
In the Sources tab right click on blink_led_zybo_bd and click on Create HDL wrapper. Leave the default option, Let Vivado manage wrapper and auto-update. Click OK.
In the Flow Navigator toolbar click the Generate Bitstream button which can be found in the Program and Debug subsection. A window pops up. Click on Save. Another window pops up. Click on Yes.
A window should pop up once the bitstream generation finished successfully. Click on Cancel.
Now click on File -> Export -> Export Hardware. Check the Include bitstream checkbox and leave the Export to: dropdown menu at <Local to project>. Click OK.
Finally, click on File -> Launch SDK. Leave both options at <Local to project>. Click OK.
This concludes the Hardware generation process.
184.108.40.206 Xilinx SDK
Click on File -> New -> Application Project to create a new project. As project name enter blink_led. Leave all other options at their default values. Click Next.
Click on the Empty Application Template and click Finish.
Once the project is sucessfully created right click on the blink_led project and click on Import.
Choose General -> File System and click Next.
Browse to the location of the downloadand and extracted GettingStartedZybo.zip file. Select main.c and click Finish.
220.127.116.11 Board Setup
Make sure that JP14 is configured to use USB as power source. Furthermore, make sure JP5 is configured to the JTAG mode. Insert a micro USB cable to J11 and connect it to your PC.
Finally, switch SW4 to the on position.
18.104.22.168 Test the Application
Right click on the blink_led project and click on Run as -> Run Configurations. Double click on Xilinx C/C++ application (GDB).
Click on the STDIO Connection tab. Check the Connect STDIO to Console checkbox. Choose the appropriate Com Port and set the Baud Rate to 115200.
Click Apply, then click Close. Now Click on Xilinx Tools -> Program FPGA. A window pops up. Leave the default options and click Program.
After the bitstream is sucessfully donwoloaded to the FPGA the DONE LED (LD10) lights up. Now click on the run Button the start the application.
The console prompts you to enter a value between 0-15. Type 8 and hit enter. LD3 starts to blink. Type 15 and hit enter. LD0- LD3 start to blink. Type 0 and hit enter. The LEDs stop to blink.