getting-started-basys3.md

@@ -26,11 +26,11 @@ This section explains how to generate the FPGA hardware bitstream using the Xili
 
 ### 5.2.1  Building the Bitstream
 
-__1. Launch Vivado:__**
+_1. Launch Vivado:_**
 
 + select **Start > All Programs > Xilinx Design Tools > Vivado 2015.4 > Vivado 2015.4**
 
-__2. Create new Project__**
+_2. Create new Project_**
 
 Click on the **Create New Project** button in the quick start menu. Click **Next**.  Enter blink_led as the Project name. Click **Next**.
 
@@ -38,7 +38,7 @@ Click on the **Create New Project** button in the quick start menu. Click **Next
 
 Select RTL Project. Make sure that the ** Do not specify sources at this time** checkbox is **not** selected. Click **Next**.
 
-![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys1.png)
+![Pic1](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys1.png)
 
 Click on the **Add Files** Button. Browse to the previously downloaded and extracted zip folder. Select **blink_led.vhd** and click **OK**. Make sure that the **Copy sources into project** checkbox is selected. And the Target language and Simulator Language is set to VHDL. Click **Next** twice.