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## 5.2 Tutorial
This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Furthermore, the Board Setup will be explained. Finally the Bitstream will be flashed onto the FPGA an the Apllication will run on the FPGA.
This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Furthermore, the Board Setup will be explained. Finally the Bitstream will be flashed onto the FPGA an the apllication will be tested.
###5.2.1 Building the Bitstream
###5.2.2 Board Setup
~~1. Launch Vivado:~~
+ select **Start > All Programs > Xilinx Design Tools > Vivado 2015.4 > Vivado 2015.4**
~~2. Create new Project~~
Click on the **Create New Project** button in the quick start menu. Click **Next**. Enter blink_led as the Project name. Click **Next**.
**Note:** Do not use spaces or special characters in the project path.
Select RTL Project. Make sure that the ** Do not specify sources at this time** checkbox is not selected. Click **Next**.
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys1.png)
###5.2.2 Run the Demo
Click on the **Add Files** Button. Browse to the previously downloaded and extracted zip folder. Select **blink_led.vhd** and click **OK**. Make sure that the **Copy sources into project** checkbox is selected. And the Target language and Simulator Language is set to VHDL. Click **Next** twice.
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys2.png)
The following istructions were be done with Windows 7 and Vivado HLx 2015.4. The installation are equivalent with an Linux operating system. At first download the "Vivado HLx 201x.y: Windows Web Installer" from the [Xilinx website](http://www.origin.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) as displayed in the following figure. In order to download the installation file you will be asked to login with your free Xilinx user account. Create an account and login. The download will automatically start.
Click on the **Add Files** Button. Browse to the previously downloaded and extracted zip folder. Select **blink_led.xdc** and click **OK**. Make sure that the **Copy constraints files into project** checkbox is selected. Click **Next**.
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation1.png)
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys3.png)
After downloading the Web Installer, start it and follow the instructions below.
In the searchbox type: **XC7A35TCPG236-1**. Select the Part and click **Next**.
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation2.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation3.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation4.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation5.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation6.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation7.png)
![](https://es.technikum-wien.at/iplat/testwiki/raw/master/vivado-toolchain/installation8.png)
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys4.png)
Now, the installation will take a few minutes. So it is time for a break and drink coffee.
Click **Finish** to finish the project creation process.
### Helpful links:
Xilinx Vivado Website: [http://www.xilinx.com/products/design-tools/vivado.html](http://www.xilinx.com/products/design-tools/vivado.html)
In the **Project Manager** toolbar on the leftside click the **Generate Bitstream** button which can be found in the Program and Debug subsection. A window pops up. Click on *Yes**.
Xilinx Vivado download: [http://www.origin.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html](http://www.origin.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html).
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys5.png)
A window should pop up once the bitstream generation finished successfully. Click on **Cancel**.
###5.2.2 Board Setup
Make sure that **JP2** is configured to use **USB** as power source. Furthermore, make sure **JP1** is configured to the **JTAG** mode. Insert a micro USB cable to JC4 and connect it to your PC. Switch SW16 to the on position. Finally, make sure that the switches **SW0 - SW15** are in the off position.
![](https://es.technikum-wien.at/iplat/testwiki/tree/master/getting-started-basys3/img/tutorial_basys6.png)
***
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