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#### [Home](https://es.technikum-wien.at/iplat/testwiki/wikis/home) | [<Vivado Toolchanin](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain)
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#### [Home](https://es.technikum-wien.at/iplat/testwiki/wikis/home) | [<Vivado Toolchanin](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain)[Getting Started - Zybo>](https://es.technikum-wien.at/iplat/testwiki/wikis/getting-started-zybo)
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... | @@ -12,17 +12,19 @@ The following section presents a tutorial for the Basys3 Development Board. |
... | @@ -12,17 +12,19 @@ The following section presents a tutorial for the Basys3 Development Board. |
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Following pre-requisites are necessary in order to work through this tutorial:
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Following pre-requisites are necessary in order to work through this tutorial:
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+ Vivado HLx 2015.4 ( see [Vivado Toolchain](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain) for an installation guide)
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+ Vivado HLx 2015.4 (see [Vivado Toolchain](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain) for an installation guide)
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+ Basys3 Development Board
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+ Basys3 Development Board
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+ micro USB cable
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+ micro USB cable
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**Note:** Vivado 2016.1 was successfully tested with this tutorial.
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### 5.1.2 Download the Design files
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### 5.1.2 Download the Design files
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An archive with the design files can be downloaded [here](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-basys3/design-files/GettingStartedBasys3.zip).
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An archive with the design files can be downloaded [here](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-basys3/design-files/GettingStartedBasys3.zip).
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## 5.2 Tutorial
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## 5.2 Tutorial
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This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Furthermore, the board setup will be explained. Finally the Bitstream will be flashed onto the FPGA an the apllication will be tested.
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This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Furthermore, the board setup will be explained. Finally, the Bitstream will be flashed onto the FPGA and the application will be tested.
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### 5.2.1 Building the Bitstream
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### 5.2.1 Building the Bitstream
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... | @@ -40,7 +42,7 @@ Select RTL Project. Make sure that the ** Do not specify sources at this time** |
... | @@ -40,7 +42,7 @@ Select RTL Project. Make sure that the ** Do not specify sources at this time** |
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Click on the **Add Files** Button. Browse to the previously downloaded and extracted zip folder. Select **blink_led.vhd** and click **OK**. Make sure that the **Copy sources into project** checkbox is selected. And the target language and simulator language is set to VHDL. Click **Next** twice.
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Click on the **Add Files** Button. Browse to the previously downloaded and extracted zip folder. Select **blink_led.vhd** and click **OK**. Make sure that the **Copy sources into project** checkbox is selected and the target language and simulator language is set to VHDL. Click **Next** twice.
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... | @@ -48,13 +50,13 @@ Click on the **Add Files** Button. Browse to the previously downloaded and extra |
... | @@ -48,13 +50,13 @@ Click on the **Add Files** Button. Browse to the previously downloaded and extra |
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In the searchbox type: **XC7A35TCPG236-1**. Select the Part and click **Next**.
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In the search box type: **XC7A35TCPG236-1**. Select the Part and click **Next**.
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Click **Finish** to finish the project creation process.
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Click **Finish** to finish the project creation process.
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In the **Project Manager** toolbar click the **Generate Bitstream** button which can be found in the Program and Debug subsection. A window pops up. Click on **Yes**.
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In the **Project Manager** toolbar click the **Generate Bitstream** button which can be found in the Program and Debug subsection. A window pops up. Click on **Yes**.
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... | @@ -69,7 +71,7 @@ Make sure that **JP2** is configured to use **USB** as power source. Furthermore |
... | @@ -69,7 +71,7 @@ Make sure that **JP2** is configured to use **USB** as power source. Furthermore |
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### 5.2.3 Test the Application
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### 5.2.3 Test the Application
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In the **Project Manager** toolbar click the **Hardware Manager** button which can be found in the Program and Debug subsection.
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In the **Project Manager** toolbar click the **Hardware Manager** button which can be found in the Program and Debug subsection.
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... | @@ -77,15 +79,15 @@ Click on the **Auto Connect** submenu of the **Open target** button. |
... | @@ -77,15 +79,15 @@ Click on the **Auto Connect** submenu of the **Open target** button. |
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Finally, click on **Programm Device -> xc7a35t_0**. A window pops up. Click on **Program**.
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Finally, click on **Program Device -> xc7a35t_0**. A window pops up. Click on **Program**.
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After the bitstream is downloaded succesfully the **DONE** LED of the Board should light up. Switch **SW0** into the up position. **LD0** starts to blink. Switch **SW0 - SW15** into the up position. **LD0-LD15** blink synchronously.
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After the bitstream is downloaded successfully the **DONE** LED of the Board should light up. Switch **SW0** into the up position. **LD0** starts to blink. Switch **SW0 - SW15** into the up position. **LD0-LD15** blink synchronously.
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This concludes the Basys3 Getting Started tutorial.
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This concludes the Basys3 Getting Started tutorial.
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***
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***
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#### [Home](https://es.technikum-wien.at/iplat/testwiki/wikis/home) |[<Vivado Toolchanin](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain) |
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#### [Home](https://es.technikum-wien.at/iplat/testwiki/wikis/home) | [<Vivado Toolchanin](https://es.technikum-wien.at/iplat/testwiki/wikis/vivado-toolchain)[Getting Started - Zybo>](https://es.technikum-wien.at/iplat/testwiki/wikis/getting-started-zybo) |
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