The following section presents a tutorial for the Basys3 Development Board.
### 5.1.1 Pre-requisites
### 5.1.1.1 Pre-requisites
Following pre-requisites are necessary in order to work through this tutorial:
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**Note:** Vivado 2016.1 was successfully tested with this tutorial.
### 5.1.2 Download the Design files
### 5.1.1.2 Download the Design files
An archive with the design files can be downloaded [here](https://es.technikum-wien.at/iplat/testwiki/raw/master/getting-started-basys3/design-files/GettingStartedBasys3.zip).
## 5.2 Tutorial
## 5.1.2 Tutorial
This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool. Furthermore, the board setup will be explained. Finally, the Bitstream will be downloaded onto the FPGA and the application will be tested.
### 5.2.1 Building the Bitstream
### 5.1.2.1 Building the Bitstream
_1. Launch Vivado:_
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A window should pop up once the bitstream generation finished successfully. Click on **Cancel**.
### 5.2.2 Board Setup
### 5.1.2.2 Board Setup
Make sure that **JP2** is configured to use **USB** as power source. Furthermore, make sure **JP1** is configured to the **JTAG** mode. Insert a micro USB cable to **JC4** and connect it to your PC. Make sure that the switches **SW0 - SW15** are in the off position.
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