An integral part of the iPlat project is the realization of an interactive, safety-related railway demonstrator (Figure 1). It will be used as development platform for future Bachelor and Master projects, as well as present a starting point for further R&D projects at the Department of Embedded Systems. The demonstrator is also planned to be presented to the broad public at events like the "Lange Nacht der Forschung" or the "Open Days" of the UAS Technikum Wien.
*Figure 1 - Railway demonstrator*
The demonstrator consists of a model train set with three tracks, two trains, a railway station and a series of signals and switches (see Figure 2). The track plan is designed in such a way as to make collisions between trains possible. There are four intersections between various tracks, as well as four switches that allow a train to change to a different track. The signals are used to prevent collisions by indicating whether a train is allowed to proceed or should stop. They are placed before each intersection and switch, as well as at the railway station.
*Figure 2 - Track plan of the railway demonstrator*
The demonstrator is a distributed system that consists of two submodules – the Operator PC and the Nodes – connected via Ethernet. The Operator PC provides a user interface to control the demonstrator and, in addition, presents media content, such as a live feed of the railway track. The Nodes, as seen in Figure 3, are responsible for motor, signal and switch control, as well as current measurement.
*Figure 3 - The hardware nodes of the railway demonstrator*
The demonstrator can operate in either autonomous (Scenario 2) or manual mode (Scenario 1). The control software on the Operator PC allows the user to select a scenario, and, in the manual mode only, control the train speed and change the position of the next switch ahead of the train. In the autonomous mode, the trains follow a predefined schedule under full control of the software.
6.1. PCB Design
The I/O PCB controls the sensors and actuators of the innovative platforms (MicroZed boards).
It also contains peripherals which are utilized by the SoC design.
Figure 4 depicts the block diagram of the PCB design including all functional blocks and circuitries.
The following pages will give an overview of the PCB design.
*Figure 4 - Block Design iPLAT Control PCB*
Railway Control Circuit
The railway control circuitry provides the main
functionalities of a track section. This includes the control of motors, switches and signals.
The motor control circuitry contains the driver circuit for the motors. The driver circuit makes
it possible to drive the motors with logic level voltages. The motor control circuitry provides the possibility to control two motors of two different track sections. The PWM is provided by the SoC design.
The switch control circuitry contains the driver circuit for the switches. The driver circuit
makes it possible to drive the switches with logic level voltages. The switch control circuitry provides the
possibility to drive two switches. The pulse required for a switching operation is provided by
the SoC design.
The signal control circuitry makes it possible to enable or disable the LED’s of each signal independently. This is achieved by multiplexing the LED’s, which saves SoC I/O’s. Furthermore, the
circuit controls the signals of two track sections. The control and data signals are
again provided by the SoC design.
Each of the motor and switch control units contains a shunt resistor required for the current
measurement circuit. This circuitry provides a voltage to the XADC pins depending on the
current. The output of the current measurement is connected to the SoC design.
Peripherals/ Add. Feature
The peripherals and additional features consist of circuitry which can be used by the user.
They are not needed for the control of a track section. The switches consist of an
8-position dip switch which can be used for configuration purposes. The four user
LED’s are used by the node application software for debug and status purposes. The EUI device
is used for device identification purposes. The user button, the additional I/O’s and the external oscillator are currently not in use.
All peripherals and additional features can be accessed from the SoC design.
6.2. SoC Design
A MicroZed board containing a Zynq-7020 device is used for the SoC design.
The task of the MicroZed board is to provide an interface to the rest of the railway system.
This interface uses Ethernet and connects the node to a local network. This way, an operator PC can control each node. The main task of the MicroZed board is to control the analog hardware located on the iPLAT control PCB. This task is performed by the SoC design.
Digital Hardware Design
Figure 5 shows the block design of the MicroZed board containing the hardware design.
*Figure 5 - Block Design iPLAT Control PCB*
Dual ARM Core
In order to communicate with the operator PC, each node implements an application software.
The processing system within the Zynq-7020 device contains a dual-core ARM Cortex-A9.
The application software is executed on one of the available ARM cores. The other ARM core
is not used in this configuration. Furthermore, the application software communicates
with the IP cores located in the PL. The communication with the Operator PC is achieved via an Ethernet based network.
General-Purpose Input/Output (GPIO) IP’s
The GPIO IP’s provide the possibility to use the DIP-switch as well as the LED’s located on the
iPLAT control PCB. The DIP-switch is used for configuration purposes and the LED’s for debug
and status purposes.
iPLAT control IP
The iPLAT control IP core contains the control elements needed to access the components
of two track sections. This also includes feedback from the analog circuit as well as node identification capabilities.
The Extended Unique Identifier (EUI) control unit makes it possible to read a 48-bit Identifier (ID) from a 1-wire device.
The ID is provided to the processing system and used as the Media Access Control (MAC) address of each node.
The motor control unit generates the Pulse Width Modulation (PWM) signals needed to control the motors.
The duty cycle can be changed in order to regulate the velocity of the trains.
Furthermore, a PWM synchronization signal is implemented, which synchronizes the PWM's of all nodes.
The motor control unit evaluates the current measurement values provided by the Xilinx Analog-Digital Converter (XADC) control
unit. Moreover, the motor control unit is instantiated twice within the IP core in order to control two different track sections.
The switch control unit generates the pulses necessary to flip the switches of the demonstrator.
Furthermore, this unit is able to track the position of a switch.
This is achieved by evaluating the current measurement values provided by the XADC.
Moreover, the switch control unit is instantiated twice within the IP core in order to control two different switches.
This unit controls the LED's of the signals of the demonstrator.
In order to do so it periodically loads the flipflops of the PCB.
The XADC receives voltage values from the current measurement circuit located on the iPLAT
control PCB. These values are provided to the motor and switch control units.
6.3. Operator PC
Figure 6 depicts an overview of the OPC software architecture, including the individual processes of the system.
Each of these processes is implemented as an operating system process. The processes communicate using dedicated interfaces.
The GUI, Railway Controller and Node Communication processes had to be developed from scratch.
*Figure 6 - OPC System Overview*
The Operator PC has a Touch LCD monitor, which is used to display the GUI. The GUI process is responsible for this task. It also implements functionality required for the application scenarios. The process uses the Qt library, which is a toolkit for GUI programming.
The Railway Controller subprocess is responsible for controlling and monitoring the railway demonstrator. Furthermore, it provides an interface to the GUI, which is used to start and stop scenarios, and to communicate error conditions to the GUI process. Moreover, this process has interfaces to the VLC player as well as the Node Communication layer.
The Node Communication layer provides low-level access to the Ethernet device of the Operator PC and implements the iPlat communication protocol. Moreover, it provides an abstracted interface to the Railway Controller, which can be used to control and monitor the railway demonstrator.
The OPC Main process monitors all other processes of the OPC software. Finally, the VLC player is used to display media content on a beamer and is comprised of an instance of the VLC media player application. It offers an interface to the Railway Controller, which can be used to control the content being displayed.
6.4. Future Work
The safety critical demonstrator developed in context of the iPLAT project is a platform that will be utilized in various research and development projects.
Thus, the platform covers different research topics ranging from multicore software development to high level synthesis.
These topics can be evaluated in the context of further master theses.
Moreover, the railway demonstrator for safety critical applications offers a platform for future research and development projects at the department.
These R&D projects might deal with topics like distributed systems, realtime systems, fault injection or coordinated debugging.
Therefore, it might be necessary to evaluate the use of newer platforms like Xilinx Ultrascale & Ultrascale+ devices.
Besides supporting research projects the demonstrator can be used as an exhibition tool at various events event such as "Lange Nacht der Forschung" or Open Days UAS Technikum Wien in order to increase the interest of the public in technology.
Furthermore, it will be used as a teaching model at different courses of the Department of Embedded Systems UAS Technikum Wien.