Commit c6552f9a authored by Christian Fibich's avatar Christian Fibich
Browse files

Updated Readme

parent 22bca3c5
......@@ -2,6 +2,9 @@
This project implements a tiny ADSR audio synthesizer in Verilog.
* Example 1: [_Still Alive_ from Portal](
* Example 2: [_Toccata and Fugue in D minor_ by JSB](
## Hardware Description ##
The synthesizer core is available in `hdl/usynth` with
......@@ -13,11 +16,16 @@ This core has the following parameters:
* `WAVEFORM` selects the implemented waveform, where
* `0` is square wave
* `1` is sine wave via DDS
The following ports are present:
* `clock`: System Clock
* `ce25`: 24 MHz Clock Enable (FIXME: name)
* `ce25`: 24 MHz Clock Enable (*FIXME: name*)
* `reset`: High-active asynchronous reset
* `enable`: One enable signal for each voice
* `play_note`: One gate signal for each voice
......@@ -27,6 +35,9 @@ The following ports are present:
* `s`: Sustain level for each voice
* `r`: Release rate for each voice
* `envelope`: Envelope generator enable for each voice
* `pwm`: The output signal. Needs external low pass filter
The synthesizer core (each voice) works as follows:
......@@ -57,12 +68,19 @@ The toplevel can be built by executing `make` in `impl/hx8k`.
## Prerequisites ##
* `python-mido`
* `pyserial` for `tools/*.py`
* `python-mido` for `tools/`
For building the toplevel:
* `yosys`, `arachne-pnr` and `icestorm`
Useful udev rule for using HX8K breakout board via `/dev/ttyHX8K`
SUBSYSTEM=="tty",ATTRS{idVendor}=="0403",ATTRS{idProduct}=="6010",ATTRS{product}=="Lattice FTUSB Interface Cable", SYMLINK+="ttyHX8K"
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