Commit 971d6500 authored by Christian Fibich's avatar Christian Fibich
Browse files

added iceZero implementation

parent 4ad4faa1
set_io clock_in_100 49
#RPI_SPI_MOSI
set_io sck 79
set_io mosi 90
#SS - IO224
set_io ss 78
# PMOD 4
# GPIO 20: 1
set_io pwm_l 1
# GPIO 21: 2
set_io gain 144
# GPIO 22: 3
set_io shutdown 143
# GPIO 23: 4
set_io pwm_r 142
# PMOD 3
# GPIO 16: 1
set_io led[0] 41
# GPIO 17: 2
set_io led[1] 39
# GPIO 18: 3
set_io led[2] 38
# GPIO 19: 4
set_io led[3] 37
# GPIO 28: 7
set_io led[4] 26
# GPIO 29: 8
set_io led[5] 29
# GPIO 30: 9
set_io led[6] 28
# GPIO 31: 10
set_io led[7] 52
module icezero_audio_top #(parameter NUM_VOICES = 3, parameter WAVEFORM = 0) ( input clock_in_100,
input sck,
input mosi,
input ss,
output gain, // 1: 6dB, 0: 12dB
output shutdown, // 1: on, 0: off
output [7:0] led,
output reg pwm_l,
output reg pwm_r);
reg [NUM_VOICES*16-1:0] freq;
reg [NUM_VOICES*16-1:0] a;
reg [NUM_VOICES*16-1:0] d;
reg [NUM_VOICES*16-1:0] s;
reg [NUM_VOICES*16-1:0] r;
assign shutdown = 1'b1;
assign gain = 1'b1;
wire locked;
wire reset;
reg [2:0] reset_sync;
wire clock;
reg [7:0] led_reg;
wire mon_ena;
wire [7:0] mon_led;
wire pwm;
reg [7:0] i;
reg [NUM_VOICES-1:0] play_note;
reg [NUM_VOICES-1:0] envelope;
reg [NUM_VOICES-1:0] enable;
reg [NUM_VOICES*8-1:0] freq_l;
reg [NUM_VOICES*8-1:0] a_l;
reg [NUM_VOICES*8-1:0] d_l;
reg [NUM_VOICES*8-1:0] s_l;
reg [NUM_VOICES*8-1:0] r_l;
pll clkgen (.clock_in(clock_in_100),.clock_out(clock),.locked(locked));
initial
reset_sync <= 3'b1;
always @(posedge clock or negedge locked) begin
if (!locked) begin
reset_sync <= 3'b1;
end else begin
reset_sync <= {reset_sync[1:0],1'b0};
end
end
always @(posedge clock) begin
pwm_l <= pwm;
pwm_r <= pwm;
end
assign reset = reset_sync[2];
usynth #(.NUM_VOICES(NUM_VOICES), .WAVEFORM(WAVEFORM)) syn
(.clock(clock), .ce25(1), .reset(reset),
.play_note(play_note[NUM_VOICES-1:0]),
.enable(enable[NUM_VOICES-1:0]),
.freq(freq[NUM_VOICES*16-1:0]),
.pwm(pwm),
.a(a[NUM_VOICES*16-1:0]),
.d(d[NUM_VOICES*16-1:0]),
.s(s[NUM_VOICES*16-1:0]),
.r(r[NUM_VOICES*16-1:0]),
.envelope(envelope[NUM_VOICES-1:0]));
wire [15:0] address;
wire [7:0] data;
wire wr;
spi2bus_top i_spi (.clock(clock),.reset(reset),
.mosi(mosi),.ss(ss),.sck(sck),
.int_address(address),
.int_wr_data(data),
.int_write(wr),
.mon_data(mon_led),
.mon_ena(mon_ena));
assign led = {2'b0, play_note & enable};
always @(posedge(clock) or posedge(reset))
begin
if (reset) begin
led_reg <= 8'hff;
for (i=0;i<NUM_VOICES;i=i+1) begin
freq_l[i*8+:8] <= 0;
a_l[i*8+:8] <= 0;
d_l[i*8+:8] <= 0;
s_l[i*8+:8] <= 0;
r_l[i*8+:8] <= 0;
freq [i*16+:16] <= 440;
a[i*16+:16] <= 16'h400;
d[i*16+:16] <= 16'h400;
s[i*16+:16] <= 16'h8000;
r[i*16+:16] <= 16'h0100;
enable <= 0;
play_note <= 0;
envelope <= 0;
end
end else begin
if (mon_ena)
led_reg <= mon_led;
if (wr)
if (address > 16'hFF) begin
enable[address[3:0]] <= data[0];
play_note[address[3:0]] <= data[1];
envelope[address[3:0]] <= data[2];
end else begin
case (address[3:0])
4'h0: freq_l[address[7:4]*8 +:8] <= data;
4'h1: freq [address[7:4]*16+:16] <= {data, freq_l[address[7:4]*8+:8]};
4'h2: a_l [address[7:4]*8 +:8] <= data;
4'h3: a [address[7:4]*16+:16] <= {data, a_l[address[7:4]*8 +:8]};
4'h4: d_l [address[7:4]*8 +:8] <= data;
4'h5: d [address[7:4]*16+:16] <= {data, d_l[address[7:4]*8 +:8]};
4'h6: s_l [address[7:4]*8 +:8] <= data;
4'h7: s [address[7:4]*16+:16] <= {data, s_l[address[7:4]*8 +:8]};
4'h8: r_l [address[7:4]*8 +:8] <= data;
4'h9: r [address[7:4]*16+:16] <= {data, r_l[address[7:4]*8 +:8]};
default : play_note <= play_note;
endcase
end
end
end
endmodule
/**
* PLL configuration
*
* This Verilog module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 100.000 MHz
* Requested output frequency: 24.000 MHz
* Achieved output frequency: 23.958 MHz
*/
module pll(
input clock_in,
output clock_out,
output locked
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0010), // DIVR = 2
.DIVF(7'b0010110), // DIVF = 22
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b011) // FILTER_RANGE = 3
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clock_in),
.PLLOUTCORE(clock_out),
);
endmodule
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