Commit 779b9ef9 authored by Christian Fibich's avatar Christian Fibich
Browse files

Bugfixes

parent 971d6500
......@@ -30,8 +30,10 @@ input int_gnt; // bus access grant signal
// baud rate configuration, see baud_gen.v for more details.
// baud rate generator parameters for 460800 baud on 24MHz clock
`define D_BAUD_FREQ 12'd192
`define D_BAUD_LIMIT 16'd433
//`define D_BAUD_FREQ 12'd192
//`define D_BAUD_LIMIT 16'd433
`define D_BAUD_FREQ 12'd256
`define D_BAUD_LIMIT 16'd6399
// baud rate generator parameters for 115200 baud on 44MHz clock
// `define D_BAUD_FREQ 12'd23
// `define D_BAUD_LIMIT 16'd527
......
......@@ -20,7 +20,7 @@ module usynth #(parameter NUM_VOICES = 3, parameter WAVEFORM = 0)
wire [15:0] sample_out [NUM_VOICES-1:0];
wire [15:0] sample [NUM_VOICES-1:0];
reg [15:0] sum;
reg [19:0] sum;
clken ce (.clock(clock),.reset(reset),
.ce25(ce25),
......@@ -33,7 +33,7 @@ module usynth #(parameter NUM_VOICES = 3, parameter WAVEFORM = 0)
generate
for (index=0; index<NUM_VOICES; index=index+1) begin : gen_voice
voice #(.WAVEFORM(WAVEFORM)) v (.clock(clock),
voice #(.WAVEFORM((index == NUM_VOICES-1) ? 4 : WAVEFORM)) v (.clock(clock),
.reset(reset),
.ce_sample(ce_sample),
.ce_timing(ce_envelope),
......@@ -50,13 +50,13 @@ module usynth #(parameter NUM_VOICES = 3, parameter WAVEFORM = 0)
endgenerate
always @(*) begin
sum = 16'h0;
sum = 19'h0;
for (i = 0; i < NUM_VOICES; i=i+1)
sum = sum + {4'b0,sample[i][15:4]};
sum = sum + sample[i];
end
pwm p (.clock(clock), .reset(reset),
.ce_pwm(ce_pwm), .sample(sum[15:8]),
.ce_pwm(ce_pwm), .sample({sum[19:11],(sum[10:0] >= 11'h400) ? 1'b1 : 1'b0}),
.out(pwm));
endmodule
......
......@@ -42,7 +42,10 @@ module envelope_generator (input wire clock,
if (ce == 1'b1) begin
if (enable == 1'b1) begin
case (adsr_state)
IDLE : adsr_state <= IDLE;
IDLE : begin
adsr_state <= IDLE;
acc <= 16'h0;
end
ATTACK: begin
if (acc == 16'hffff)
......@@ -52,10 +55,11 @@ module envelope_generator (input wire clock,
end
DECAY: begin
if (acc == s_sampled)
if (acc == s_sampled) begin
acc <= s_sampled;
adsr_state <= SUSTAIN;
else
acc <= ((acc - d_sampled) < s_sampled) ? s_sampled : acc - d_sampled;
end else
acc <= (d_sampled > acc || (acc - d_sampled) < s_sampled) ? s_sampled : acc - d_sampled;
end
SUSTAIN: begin
......@@ -68,7 +72,7 @@ module envelope_generator (input wire clock,
if (acc == 16'h0000)
adsr_state <= IDLE;
else
acc <= (acc <= r_sampled) ? 16'h0000 : acc - r_sampled;
acc <= (r_sampled > acc) ? 16'h0000 : acc - r_sampled;
end
default: begin
......
......@@ -7,9 +7,9 @@ module mixer (input wire clock, input wire reset,
wire [31:0] scale;
wire [15:0] sample_next;
assign inv = (tone[15:8] != 8'b0) ? (tone[15:0] - 16'h8000) : (16'h8000 - tone[15:0]);
assign inv = tone; //(tone[15:8] != 8'b0) ? (tone[15:0] - 16'h8000) : (16'h8000 - tone[15:0]);
assign scale = {16'b0, inv} * {16'b0, envelope[15:0]};
assign sample_next = (tone[15:8] != 8'b0) ? (scale[31:16] + 16'h8000) : (16'h8000 - scale[31:16]);
assign sample_next = scale[31:16];
always @ (posedge clock or posedge reset)
begin
......
module pwm (input wire clock,
input wire reset,
input wire ce_pwm,
input wire [7:0] sample,
input wire [9:0] sample,
output wire out);
reg [7:0] pwm_cnt;
reg [9:0] pwm_cnt;
reg pwm_out;
reg [7:0] sample_reg;
reg [9:0] sample_reg;
always @ (posedge clock or posedge reset)
begin
if (reset == 1'b1) begin
pwm_cnt <= 8'b0;
pwm_cnt <= 10'b0;
pwm_out <= 1'b0;
sample_reg <= 8'b0;
sample_reg <= 10'b0;
msb = 1'b0;
end else if (ce_pwm == 1'b1) begin
pwm_cnt <= pwm_cnt + 1;
if (pwm_cnt == 0)
if (pwm_cnt == 10'b1111111111)
sample_reg <= sample;
if (pwm_cnt >= sample)
pwm_out <= 1'b0;
if (pwm_cnt[9])
pwm_out <= sample_reg[9];
else if (pwm_cnt[8])
pwm_out <= sample_reg[8];
else if (pwm_cnt[7])
pwm_out <= sample_reg[7];
else if (pwm_cnt[6])
pwm_out <= sample_reg[6];
else if (pwm_cnt[5])
pwm_out <= sample_reg[5];
else if (pwm_cnt[4])
pwm_out <= sample_reg[4];
else if (pwm_cnt[3])
pwm_out <= sample_reg[3];
else if (pwm_cnt[2])
pwm_out <= sample_reg[2];
else if (pwm_cnt[1])
pwm_out <= sample_reg[1];
else
pwm_out <= 1'b1;
pwm_out <= sample_reg[0];
end
end
......
......@@ -7,17 +7,24 @@ module tone_generator #(parameter WAVEFORM = 0)
reg [12:0] phacc;
reg [7:0] wavetable [4095:0];
reg [15:0] wave_out;
wire [15:0] wave_out;
wire [11:0] wavetable_addr;
reg [7:0] wavetable_out;
reg [23:0] lfsr;
reg phacc_10_last;
always @(posedge clock or posedge reset)
begin
if (reset) begin
phacc <= 13'b0;
lfsr <= 24'b1;
phacc_10_last <= 1'b0;
end else if (ce) begin
phacc_10_last <= phacc[10];
phacc <= phacc + {1'b0, freq[11:0]}; // Don't allow increments > 1/2
if (2'b10 == {phacc[10],phacc_10_last})
lfsr <= {lfsr[21:0],lfsr[22]^lfsr[17]^(phacc[12])};
end
end
......@@ -29,9 +36,15 @@ module tone_generator #(parameter WAVEFORM = 0)
generate
if (WAVEFORM == 0) /* Square */
assign wave_out[15:8] = (phacc[12]) ? 8'hff : 8'h00;
assign wave_out[15:8] = (phacc[12:11] == 2'b01) ? 8'hff : 8'h00;
else if (WAVEFORM == 1) /* SINE */
assign wave_out[15:8] = (phacc[12]) ? 8'hff-wavetable_out : wavetable_out;
else if (WAVEFORM == 2) /* SAWTOOTH */
assign wave_out[15:8] = phacc[12:5];
else if (WAVEFORM == 3) /* TRIANGLE */
assign wave_out[15:8] = (phacc[12]) ? 8'hff-phacc[11:4] : phacc[11:4];
else if (WAVEFORM == 4) /* NOISE */
assign wave_out[15:8] = {lfsr[22],lfsr[20],lfsr[16],lfsr[13],lfsr[11],lfsr[7],lfsr[4],lfsr[2]};
endgenerate
assign wave_out[7:0] = 8'b0;
......
This diff is collapsed.
`timescale 1ns/100ps
module synth_basys3 (input wire clock100, input wire reset,
input wire key, output wire pwm, input wire [15:0] sw);
reg [1:0] key_sync;
reg [15:0] sw_sync_0;
reg [15:0] sw_sync_1;
reg [1:0] ce25_count;
reg ce25;
reg [9:0] key_debounce_count;
reg reg_key;
synth s (.clock(clock100), .ce25(ce25), .reset(reset),
.play_note(reg_key), .out(pwm), .freq(sw_sync_1), .envelope(sw[15]),
.a(16'h0800),.d(16'h0800),.s(16'hC000),.r(16'h1000));
always @ (posedge clock100 or posedge reset)
begin
if (reset == 1'b1) begin
ce25_count <= 2'b11;
ce25 <= 1'b0;
end else begin
ce25 <= 1'b0;
ce25_count <= ce25_count - 2'b01;
if (ce25_count == 2'b00) begin
ce25 <= 1'b1;
end
end
end
always @ (posedge clock100 or posedge reset)
begin
if (reset == 1'b1) begin
key_sync <= 2'b0;
key_debounce_count <= 10'b0;
sw_sync_0 <= 16'b0;
sw_sync_1 <= 16'b0;
reg_key <= 1'b0;
end else begin
key_sync <= {key_sync[0], key};
sw_sync_1 <= sw_sync_0;
if (ce25 == 1'b1) begin
key_debounce_count <= key_debounce_count + 1'b1;
if (key_debounce_count[9] == 1'b1) begin
key_debounce_count <= 10'b0;
reg_key <= key_sync[1];
sw_sync_0 <= sw;
end
end
end
end
endmodule
......@@ -23,21 +23,21 @@ set_io pwm_r 142
# PMOD 3
# GPIO 16: 1
set_io led[0] 41
set_io led[0] 26
# GPIO 17: 2
set_io led[1] 39
set_io led[1] 29
# GPIO 18: 3
set_io led[2] 38
set_io led[2] 28
# GPIO 19: 4
set_io led[3] 37
set_io led[3] 52
# GPIO 28: 7
set_io led[4] 26
set_io led[4] 41
# GPIO 29: 8
set_io led[5] 29
set_io led[5] 39
# GPIO 30: 9
set_io led[6] 28
set_io led[6] 38
# GPIO 31: 10
set_io led[7] 52
set_io led[7] 37
module icezero_audio_top #(parameter NUM_VOICES = 3, parameter WAVEFORM = 0) ( input clock_in_100,
module icezero_audio_top #(parameter NUM_VOICES = 7, parameter WAVEFORM = 2) ( input clock_in_100,
input sck,
input mosi,
input ss,
......
......@@ -26,12 +26,15 @@ def note_on(port,voice):
def note_off(port,voice):
write(port,0x100+voice,[5])
def chan_off(port,voice):
write(port,0x100+voice,[0])
def freq(note):
return (2.0**((note - 69)/12.0))*440.0;
def sigint_handler(num,frame):
for v in range(0,8):
note_off(port,v)
chan_off(port,v)
port.close()
sys.exit(0)
......@@ -78,12 +81,12 @@ if __name__=="__main__":
signal.signal(signal.SIGINT,sigint_handler)
voices = [None]*8
voices = [None]*6
#write(port,0x100,[5]*8) # Voices on + envelope
for v in range(0,8):
note_off(port,v)
chan_off(port,v)
set_freq(port,v,440)
set_adsr(port,v,0x400,0x400,0x4000,0x100)
......
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