Commit 22bca3c5 authored by Christian Fibich's avatar Christian Fibich
Browse files

Repo Cleanup

parent 2235a332
# uSynth Audio Synthesizer #
This project implements a tiny ADSR audio synthesizer in Verilog.
## Hardware Description ##
The synthesizer core is available in `hdl/usynth` with
`usynth.v` being the top level.
This core has the following parameters:
* `NUM_VOICES` selects the number of available voices (i.e., notes that can be played at the same time)
* `WAVEFORM` selects the implemented waveform, where
* `0` is square wave
* `1` is sine wave via DDS
The following ports are present:
* `clock`: System Clock
* `ce25`: 24 MHz Clock Enable (FIXME: name)
* `reset`: High-active asynchronous reset
* `enable`: One enable signal for each voice
* `play_note`: One gate signal for each voice
* `freq`: Frequency for each voice
* `a`: Attack rate for each voice
* `d`: Decay rate for each voice
* `s`: Sustain level for each voice
* `r`: Release rate for each voice
* `envelope`: Envelope generator enable for each voice
The synthesizer core (each voice) works as follows:
* The `tone_generator` module generates a signal of the specified
frequency and waveform at maximum amplitude
* When `envelope` is `1` for the voice, this signal is mixed with
the envelope generated by the `envelope_generator`.
* Until `play_note` is 0, nothing happens
* When `play_note` becomes 1, the amplitude is incremented
every _N_ samples by the _Attack Rate_
* When the maximum amplitude is reached, the envelope generator
decrements the amplitude every _N_ samples by the _Decay Rate_
* Until the `play_note` signal becomes 0, the signal is held at
the _Sustain Level_.
* When the `play_note` signal becomes 0, the envelope generator
decrements the amplitude every _N_ samples by the _Release Rate_
## Toplevel ##
The top level design in `impl/hx8k` implements an 8 voice square
wave synthesizer for the Lattice HX8K breakout board. This synthesizer
can be controlled via the UART2BUS core and a simple bus interface.
The `tools/` script uses `python-mido` to play standard
midi files using this demo design.
The toplevel can be built by executing `make` in `impl/hx8k`.
## Prerequisites ##
* `python-mido`
For building the toplevel:
* `yosys`, `arachne-pnr` and `icestorm`
.PHONY : all clean prog
all : prog
audio.blif: *.v uart2bus/*.v usynth/*.v
audio.blif: *.v $(ROOT_DIR)/hdl/uart2bus/*.v $(ROOT_DIR)/hdl/usynth/*.v
yosys -v4 -l synth.log -p 'synth_ice40 -top hx8k_audio_top -blif $@' $^
audio.asc: audio.blif audio.pcf
......@@ -2,4 +2,14 @@ set_io clock_in J3
set_io tx B12
set_io rx B10
set_io pwm C16
set_io led[0] B5
set_io led[1] B4
set_io led[2] A2
set_io led[3] A1
set_io led[4] C5
set_io led[5] C4
set_io led[6] B3
set_io led[7] C3
module hx8k_audio_top #(parameter NUM_VOICES = 8, parameter WAVEFORM = 0) ( input clock_in,
input rx,
output tx,
output [7:0] led,
output pwm);
reg [NUM_VOICES*16-1:0] freq;
......@@ -64,6 +65,8 @@ module hx8k_audio_top #(parameter NUM_VOICES = 8, parameter WAVEFORM = 0) ( inpu
assign led = play_note & enable;
always @(posedge(clock) or posedge(reset))
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment